Survey of Low Power Testing of VLSI Circuits

Power Minimisation Techniques for Testing Low Power VLSI Circuits

Low Power Testing of VLSI Circuits: Problems and Solutions

Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to the circuit reliability. Moreover, it may be responsible for cost, performance verification as well as technology related problems and can dramatically shorten the battery life when on-line testing is considered. In th...

Optimization Techniques for Low Power VLSI Circuits

Power dissipation has emerged as an important design parameter in the design of microelectronic circuits, especially in portable computing and personal communication applications. In this paper, we survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered.

A survey of power estimation techniques in VLSI circuits

With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and e cient power estimation during the design phase is required in order to meet the power speci cations without a costly redesign process. In this paper, we present a review/tutorial of the power estimation techniqu...

Glitch Power Minimization Techniques in Low Power VLSI Circuits

Due to miniaturization of circuits mobility degradation, velocity saturation and power dissipation issues are critical in the design of VLSI circuits. In this paper various techniques to minimize power dissipation due to glitches are discussed. Total power consumption consists of two major parts like static power consumption and dynamic power consumption. In the total power, the static power is...